Method of reducing stress corrosion induced voiding of patterned metal layers

ABSTRACT

Stress corrosion induced voiding of patterned metal layers is avoided or substantially reduced by removing etching residues before gap filling. Embodiments include etching an Al or Al alloy layer employing fluorine and/or chlorine chemistry, wet cleaning, treating with a nitrogen-containing plasma at a temperature of at least about 400° C. and gap filling with a dielectric material, e.g. HDP oxide by HDP CVD.

RELATED APPLICATIONS

[0001] This application contains subject matter similar to subjectmatter disclosed in copending U.S. patent application Ser. No. ______,filed on ______ (Our Docket No. 50100-997).

TECHNICAL FIELD

[0002] The present invention relates to a method of manufacturing amulti-metal layer semiconductor device exhibiting improvedelectromigration resistance. The invention has particular applicabilityin manufacturing high density multi-metal layer semiconductor deviceswith design rules of 0.18 micron and under.

BACKGROUND ART

[0003] The escalating requirements for high density and performanceassociated with ultra large scale integration semiconductor devicesrequire design rules of 0.18 micron and under, increased transistor andcircuit speeds, high reliability and increased manufacturing throughput.The reduction of design features to 0.18 micron and under challenges thelimitations of conventional interconnection technology.

[0004] Conventional subtractive etching methodology comprises forming afirst inter-layer dielectric on a semiconductor substrate, typicallymonocrystalline silicon, with conductive contacts formed therein forelectrical connection with an active region on the semiconductorsubstrate, such as a source/drain region. A metal layer, such asaluminum or an aluminum alloy, is deposited on the first inter-layerdielectric, and a photoresist mask is formed on the metal layer todefine a desired conductive pattern. The metal layer is then etchedthrough the photoresist mask to form the conductive pattern comprisingmetal features separated by gaps, such as a plurality of metal lineswith interwiring spacings therebetween. A dielectric layer is thenapplied to the resulting conductive pattern to fill in the gaps and thesurface is planarized, as by conventional etching or chemical-mechanicalpolishing (CMP) planarization techniques.

[0005] A through-hole is typically formed in an overlying inter-layerdielectric to expose an underlying metal feature for interconnection. InU.S. patent application Ser. No. 08/924,133 filed on Sep. 5, 1997, ahigh density plasma (HDP) oxide is employed as a gap filling material toachieve superior conformal coverage vis-à-vis SOG and conventionaloxides deposited by plasma enhanced chemical vapor deposition. HDPoxides also exhibit higher density than SOG, greater chemical stability,and greater etch resistance. The entire disclosure of U.S. patentapplication Ser. No. 08/924,133 is incorporated herein by reference.

[0006] As shown in FIGS. 1 and 2, conventional practices comprisedepositing metal layer 11 on interlayer dielectric 10, which istypically formed on a semiconductor substrate containing an activeregion with transistors (not shown). After photolithography, etching isconducted to form a patterned metal layer comprising metal features 11a, 11 b, 11 c and 11 d with gaps therebetween. A dielectric material 12,such as spin on glass (SOG), is typically deposited to fill in the gapsbetween the metal features, and baked at a temperature of about 300° C.to about 450° C., for a period of time up to about two hours, dependingupon the particular SOG material employed. At a design rule of about0.18 micron, metal lines shrink to a width of about 0.25 micron andinterwiring spacings shrink to a width of about 0.3 micron. At suchreduced dimensions, it is extremely difficult to satisfactorily fill inthe interwiring spacings voidlessly and obtain adequate step coverage toform a reliable interconnection structure.

[0007] Conventional metal features comprise a composite layercomprising, for example, a lower metal barrier layer, such as titanium(Ti), an intermediate or primary conductive layer, e.g. aluminum or analuminum alloy, and an anti-reflective coating (ARC) thereon, such astitanium nitride(TiN). Such a composite metal line is conventionallypatterned into a plurality of metal features, e.g. conductive lines,employing anisotropic etching, typically with fluorine and/or chlorinechemistry. Subsequent to etching, a wet cleaning procedure is conductedin an attempt to remove etching residue. Such conventional wet cleaningtypically comprises treatment with a solvent. Subsequent to cleaning,the gap filling dielectric layer is deposited to fill the gap betweenthe metal features.

[0008] In conducting such conventional procedures, particularly as thedesign rule is scaled down to 0.18 micron and under, it is extremelydifficult to effectively remove etching residues formed duringpatterning. Such etching residues are believed to attack the sidesurfaces of metal features and form voids. For example, ammonia from thecleaning solution can combine with residual chlorine from the etchingprocess to form hydrochloric acid which attacks the side surfaces of themetal feature. Such corrosion of the side surfaces also results invoiding upon gap filling, thereby significantly increasingelectromigration and, hence, significantly limiting the lifetime of themetal line as well as degrading device performance.

[0009] Electromigration in a metal interconnection line can becharacterized by the movement of ions induced by a high electricalcurrent density. Miniaturization demands long interconnects having smallcontacts and small cross-sections. Such reduced feature sizes arecharacterized by high electrical current density and, consequently,increased metalization electromigration failures. The increasedsusceptibility to electromigration as design features shrink isexacerbated by the corrosion of side surfaces of metal lines by etchingresidues and the formation of voids.

[0010] There exists a need for interconnect methodology enabling theformation of patterned metal lines without residues on side surfaces ofthe metal lines and without the generation of voids. There exists aparticular need for interconnect methodology enabling gap fillingpatterned metal lines in semiconductor devices having a design rule ofabout 0.18 micron and under without an attendant decrease inelectromigration resistance.

DISCLOSURE OF THE INVENTION

[0011] An advantage of the present invention is a method ofmanufacturing a semiconductor device having an interconnection structurewith improved electromigration resistance.

[0012] Another advantage of the present invention is a method ofmanufacturing a semiconductor device with a design rule of about 0.18micron and under, without any significant corrosion of the side surfacesof metal features and without any substantial void formation upon gapfilling, thereby improving electromigration resistance.

[0013] Additional advantages and other features of the present inventionwill be set forth in part in the description which follows and in partwill become apparent to those having ordinary skill in the art uponexamination of the following or may be learned from the practice of thepresent invention. The advantages of the present invention may berealized and obtained as particularly pointed out in the appendedclaims.

[0014] According to the present invention, the foregoing and otherobjects are achieved in part by a method of manufacturing asemiconductor device, the method comprising: forming a patterned metallayer comprising metal features having side surfaces with gapstherebetween; and treating the patterned metal layer with anitrogen-containing plasma.

[0015] Embodiments of the present invention include forming a conductiveline comprising a lower metal layer, such as W or Ti, a primaryconductive metal layer such as aluminum or an aluminum alloy thereon andan ARC, such as Ti—TiN thereon, anisotropically etching using chlorineand/or fluorine chemistry to form a pattern of metal features separatedby interwiring spaces, wet cleaning and subsequently treating thecleaned patterned metal line with a nitrogen-containing plasma at atemperature of at least about 400° C. to remove or substantially reduceetching residues and/or compounds which attack the side surfaces of themetal features. Embodiments further include gap filling with HDP oxide.

[0016] Additional advantages of the present invention will becomereadily apparent to those skilled in this art from the followingdetailed description, wherein only the preferred embodiment of thepresent invention is shown and described, simply by way of illustrationof the best mode contemplated for carrying out the invention. As will berealized, the invention is capable of other and different embodiments,and its several details are capable of modifications in various obviousrespects, all without departing from the invention. Accordingly, thedrawings and description are to be regarded as illustrative in nature,and not as restrictive.

BRIEF DESCRIPTION OF DRAWINGS

[0017]FIGS. 1 and 2 schematically illustrate sequential phases of aconventional method.

[0018]FIG. 3 illustrates the sidewall corrosion problem attendant uponconventional methodology.

[0019]FIGS. 4 and 5 schematically illustrate sequential phases accordingto an embodiment of the present invention.

DESCRIPTION OF THE INVENTION

[0020] The present invention addresses and solves the side surfacecorrosion problem encountered in patterning and gap filling closelyspaced apart metal lines in an effort to satisfy the imposing demandsfor increased density in semiconductor devices. For example, aconductive layer is deposited and patterned on inter-layer dielectric 30to form at least one metal feature comprising a lower barrier layer 31,a primary conductive layer 32 and an ARC 33, as shown in FIG. 3. As aresult of anisotropic etching to pattern the metal layer and/orsubsequent wet cleaning, residues are formed which attack the sidesurfaces of the metal feature, as by causing corrosion indicated byreference numeral 34, thereby creating electromigration problems.Moreover, after gap filling with dielectric material 35, such as HDPoxide, voids 36 are formed. Additional problems are created upon formingan interconnection between metal features on different levels employingborderless vias, because of the difficulty in filling high aspect ratioborderless via holes exacerbated by concavity 34.

[0021] In accordance with embodiments of the present invention, theforegoing and other problems are solved by exposing the patterned metallayer to a nitrogen-containing plasma prior to depositing the gapfilling dielectric material. Embodiments of the present inventioninclude etching a composite conductive layer, wet cleaning subsequent toetching, and then treating the cleaned patterned metal layer with anitrogen-containing plasma at a temperature of at least about 400° C.,prior to depositing a dielectric gap filing layer, such as HDP oxide.The exact mechanism underpinning the advantageous reduction in corrosionof the side surfaces of the metal feature and voiding, such as stresscorrosion induced voiding, is not known with certainty. However, it isbelieved that treatment with a nitrogen-containing plasma effectivelyremoves any residues formed as a result of etching and/or wet cleaning,thereby avoiding corrosive attack of the side surfaces of the metalfeature.

[0022] Embodiments of the present invention comprise forming aconventional composite metal layer, etching the composite layer in aconventional manner employing, chlorine and/or fluorine chemistry, wetcleaning the patterned metal layer, as with a solvent, and then treatingthe patterned metal layer with the nitrogen-containing plasma at atemperature of about 350° C. to about 420° C., for about 20 seconds toabout 70 seconds. Given the objectives of the present invention andguidance set forth herein, the optimum nitrogen-containing plasmatreating conditions can be determined in a particular situation. Forexample, it was found suitable to employ a nitrogen flow rate of about1,000 to about 5,000 sccm, a source power of about 500 to about 2,500watts, a bias power of about 200 to about 2,800 watts, a temperature ofabout 350 to about 420° C. and a pressure of about 1.4 to about 3.0Torr, for about 20 to about 70 seconds. Advantageously, treatment of thepatterned metal layer with the nitrogen-containing plasma and depositionof the HDP oxide can be conducted in the same tool.

[0023] Embodiments of the present invention include forming andpatterning a composite metal layer comprising a lower barrier layer,such as Ti, W, Ti—W, titanium nitride (TiN) or titanium-titanium nitride(Ti—TiN), an intermediate primary conductive layer, such as aluminum oran aluminum alloy, e.g. an aluminum alloy containing up to about 1.5 at.% copper, and an ARC, e.g. Ti—TiN. In practicing embodiments of thepresent invention, any gap filling dielectric material can be employedsubsequent to treatment with a nitrogen-containing plasma. Suitableresults have been achieved by depositing a HDP oxide, as by high densityplasma chemical vapor deposition. In this respect, the methodologydisclosed in co-pending U.S. patent application Ser. No. 08/924,133, canbe employed.

[0024] An embodiment of the present invention is schematicallyillustrated in FIGS. 4 and 5, wherein similar elements bear similarreference numerals. Adverting to FIG. 4, a metal feature is formed oninterlayer dielectric 40 in a conventional manner by depositing acomposite conductive layer and anisotropically etching employingfluorine and/or chlorine chemistry. The metal feature comprises a lowerbarrier layer, e.g. Ti, a primary conductive layer 42, e.g. aluminum oraluminum alloy, and an ARC 43, e.g. TiN. After patterning, conventionalwet cleaning is performed employing a solvent. After wet cleaning, thepatterned metal layer is treated with a nitrogen-containing plasma,indicated by arrows 45, to effectively remove residues from precedingsteps, e.g., etching and/or wet cleaning. Subsequently, a dielectric gapfilling material 50, e.g. HDP oxide, is deposited. As a result of thetreatment with the nitrogen-containing plasma (45, FIG. 4), harmfulresidues are removed thereby avoiding corrosion of the side surfaces 44of the metal feature. Consequently, voiding is reduced andelectromigration resistance is improved.

[0025] The present invention provides methodology enabling the efficientmanufacture of high density semiconductor devices having a plurality,e.g. five or more, patterned metal layers, with an interconnectionsystem having a design rule of about 0.18 micron and under. Inaccordance with the present invention, an interconnect system, includingborderless vias, can be formed with improved electromigrationresistance.

[0026] In accordance with embodiments of the present invention, gapsbetween the metal features, e.g., metal lines, are filled aftertreatment with a nitrogen-containing plasma by depositing a suitabledielectric gap filling material, such as an HDP oxide employingHDP-chemical vapor deposition. The resulting HDP oxide is relativelyconformal. Accordingly, embodiments of the present invention alsoinclude depositing another dielectric layer, such as an oxide derivedfrom tetraethyl orthsilicate (TEOS) after depositing the HDP oxide, andplanarizing by CMP.

[0027] The present invention advantageously enables formation of highlyreliable interconnect systems with improved electromigration resistanceand reduced voiding. The present invention is applicable to theproduction of various types of semiconductor devices, particularly highdensity multi-level semiconductor devices with a design rule of abut0.18 micron and under, exhibiting high speed characteristics andimproved reliability. The present invention is cost effective and caneasily be integrated into conventional process flows employingconventional equipment.

[0028] In carrying out embodiments of the present invention, the metallayers can be formed of any metal typically employed in manufacturingsemiconductor devices, such as aluminum, aluminum alloys, copper, copperalloys, gold, gold alloys, silver, silver alloys, refractory metals,refractory metal alloys, and refractory metal compounds. The metallayers can be formed by conventional metallization techniques, such asvarious types of CVD processes, including low pressure chemical vapordeposition (LPCVD), and plasma enhanced chemical vapor deposition(PEVD). Normally, when high melting metal point melts such a tungstenare deposited, CVD techniques are employed. Low melting points metals,such as aluminum and aluminum-base alloys, including aluminum-copperalloys, can also be deposited by melting, sputtering, or physical vapordeposition (PVD).

[0029] In the previous descriptions, numerous specific details are setforth, such as specific materials, structures, chemicals, processes,etc., in order to provide a thorough understanding of the presentinvention. However, it should be recognized the present invention can bepracticed without resorting to the details specifically set forth. Inother instances, well known processing structures have not beendescribed in detail in order not to unnecessarily obscure the presentinvention.

[0030] Only the preferred embodiment of the invention and an example ofits versatility are shown and described in the present disclosure. It isto be understood that the invention is capable of use in various othercombinations and environments and is capable of changes or modificationswithin the scope of the inventive concept as expressed herein.

What is claimed is:
 1. A method of manufacturing a semiconductor device,the method comprising: forming a patterned metal layer comprising metalfeatures having side surfaces with gaps therebetween; and treating thepatterned metal layer with a nitrogen-containing plasma.
 2. The methodaccording to claim 1 , comprising sequentially: forming a metal layer;etching the metal layer to form the patterned metal layer; wet cleaningthe patterned metal layer; treating the patterned metal layer with anitrogen-containing plasma; and depositing a dielectric material in thegaps.
 3. The method according to claim 2 , comprising depositing a highdensity plasma oxide by high density plasma chemical vapor deposition tofill the gaps.
 4. The method according to claim 3 , comprising treatingthe patterned metal layer with the nitrogen-containing plasma anddepositing the high density plasma oxide in the same tool.
 5. The methodaccording to claim 2 , comprising wet cleaning with a solvent.
 6. Themethod according to claim 2 , comprising etching the metal layeremploying an etching recipe comprising fluorine and/or chlorine.
 7. Themethod according to claim 6 , wherein: etching and/or wet cleaningresult in the formation of residues which can attack the side surface ofthe metal feature; and the nitrogen-containing plasma treatmentsubstantially removes the residues before depositing the dielectricmaterial.
 8. The method according to claim 6 , comprising treating thepatterned metal layer with the nitrogen-containing plasma at atemperature of at least about 400° C.
 9. The method according to claim 8, comprising treating the patterned metal layer with thenitrogen-containing plasma at a: nitrogen flow rate of about 1,000 toabout 5,000 sccm; source power of about 500 to about 2,500 watts; biaspower of about 200 to about 2,800 watts; temperature of about 350 toabout 420° C.; and pressure of about 1.4 to about 3.0 Torr.
 10. Themethod according to claim 9 , comprising treating the patterned metallayer with the nitrogen-containing plasma for about 20 to about 70seconds.
 11. The method according to claim 1 , wherein the metal layeris a composite comprising: a lower barrier layer; an intermediateprimary conductive layer; and an anti-reflective coating on theintermediate layer.
 12. The method according to claim 11 , wherein: thebarrier layer comprises titanium, titanium-tungsten, titanium nitride,or titanium-titanium nitride; the intermediate primary conductive layercomprises aluminum or an aluminum alloy; and the anti-reflective coatingcomprises titanium-titanium nitride.
 13. The method according to claim12 , wherein the barrier layer comprises titanium nitride.
 14. Themethod according to claim 12 , wherein the aluminum alloy containscopper.